2025
O. Oulkaid, B. Ferres, M. Moy, P. Raymond, M. Khosravian.
Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. pp.1–14.
[pdf,
bib]
B. Ferres, O. Oulkaid, M. Moy, G. Radanne, L. Henrio, P. Raymond, M. Khosravian.
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits.
In ACM Transactions on Design Automation of Electronic Systems. pp.1–28.
[pdf,
bib]
2024
O. Oulkaid, B. Ferres, M. Moy, P. Raymond, M. Khosravian, L. Henrio, G. Radanne.
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving.
In Design Automation and Test in Europe. Valencia, Spain. pp.1–6.
[pdf,
bib]
2023
B. Ferres, O. Oulkaid, L. Henrio, M. Khosravian, M. Moy, G. Radanne, P. Raymond.
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory.
In Design Automation and Test in Europe. Antwerp, Belgium. pp.1–2.
[pdf,
bib]