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   Oussama Oulkaid
   PhD Student

About

Since October 2022, I am conducting a PhD thesis at LIP, Verimag, and Aniah, on formal models of integrated circuits for transistor level electrical verification, under the supervision of Matthieu Moy, Pascal Raymond, Mehdi Khosravian, and Bruno Ferres.

Publications

O. Oulkaid, B. Ferres, M. Moy, P. Raymond, M. Khosravian. (2025). Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. pp.1–14. [pdf, bib]

B. Ferres, O. Oulkaid, M. Moy, G. Radanne, L. Henrio, P. Raymond, M. Khosravian. (2025). A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits. In ACM Transactions on Design Automation of Electronic Systems. pp.1–28. [pdf, bib]

O. Oulkaid, B. Ferres, M. Moy, P. Raymond, M. Khosravian, L. Henrio, G. Radanne. (2024). A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving. In Design Automation and Test in Europe. Valencia, Spain. pp.1–6. [pdf, bib]

B. Ferres, O. Oulkaid, L. Henrio, M. Khosravian, M. Moy, G. Radanne, P. Raymond. (2023). Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory. In Design Automation and Test in Europe. Antwerp, Belgium. pp.1–2. [pdf, bib]

Teaching

Teaching Assistant in Lionel Rieg's course: Conception et Exploitation des Processeurs. RISC-V processor design (project). Grenoble INP – Ensimag. Spring 2024 and 2025.

Teaching Assistant in Laurence Pierre's course: Modélisation des Systèmes Numériques. Circuit design labs in VHDL (Master 2). Université Grenoble Alpes. Fall 2023 and 2024.

Contact

oussama.oulkaid@univ-grenoble-alpes.fr